Platform: VHDL/VERILOG

The SRL FIFO is a group of First In First Out (FIFO’s) registers, based upon the shift
register principle. These are aimed in particular at the Xilinx range of FPGA’s that
have very efficient shift register implementations, known as SRL.
Features:
· Standard VHDL, no instantiated blocks
· Small size, 8 bit wide , 32 deep FIFO uses 19 LUTs in a Spartan 3A
· Operates from a wide range of input clock frequencies
· Static synchronous design
· Fully synthesizable