Electronics Projects: VLSI
All electronics/ electrical projects are listed here.
JTAG Test Access Port (TAP)
Last changed: 1 year 34 weeks ago
Platform: VHDL/VERILOG
This implementation of the Test Access Port (TAP) is fully IEEE 1149.1 compliant. It includes a TAP controller, a 4-bit instruction register and three test data registers: idcode register, bypass register and boundary scan register. Boundary scan register is connected to eight pins (2 inputs, 2 outputs, 2 tristatable outputs and 2 bidirectional pins).
SRL FIFO
Last changed: 1 year 34 weeks ago
Platform: VHDL/VERILOG
The SRL FIFO is a group of First In First Out (FIFO’s) registers, based upon the shift
register principle. These are aimed in particular at the Xilinx range of FPGA’s that
have very efficient shift register implementations, known as SRL.
Features:
· Standard VHDL, no instantiated blocks
· Small size, 8 bit wide , 32 deep FIFO uses 19 LUTs in a Spartan 3A
· Operates from a wide range of input clock frequencies
· Static synchronous design
· Fully synthesizable
Tan inverse generation using CORDIC algorithm
Last changed: 1 year 34 weeks ago
Platform : VHDL/VERILOG
Today in many DSP application there is always a need the tan inverse value (theta) for a specified value. Here we have implemented the same with the algorithm CORDIC.
It takes less hardware than the traditional LUT method . Only the disadvantage is its initial latency. but that can be overcome by having a pipelined structure.
Vhdl implementation of digital FIR filters using fast FIR Algorithm
Last changed: 1 year 34 weeks ago
Platform: VHDL/VERILOG
FIR filters are the building block of digital processing system. We have
implemented a low pass filter using fast FIR algorithm in Vhdl and MATLAB which is an area efficient and also consumes less power than the traditional filter. We have verified the results in both the environment.